A digital-to-analogue converter (DAC) generates an analogue quantity, such as a current, in response to a digital code. The DAC is normally divided into a number of segments each of which generates a quantity in proportion to the weight of the bit in the code corresponding to the segment. The total analogue quantity is the sum of the separate quantities generated at the output from each segment in response to the input code.
The analogue quantity generated at the output from each segment has to be maintained in a precise ratio relative to that in other segments in proportion to the relative code weight, in order that the linearity of the DAC be maintained. The most critical factor, when circuits which compensate other sources of error are adopted, is the resistance of the reference resistors in each segment. In particular, the resistance values of resistors are known to drift differentially both with operating temperature and with time due to aging. Such drift limits the precision of the analogue quantities generated and so the precision that can be ascribed to a DAC.
The best (technologically realistic) resistors currently available have temperature tracking coefficients of the order of 1 ppm per .degree.C. A DAC specified as operable over a range of .+-.50.degree. C. will therefore be limited to 14 bit accuracy using such resistors, and the temperature of a DAC capable of 20 bit accuracy needs to be controlled to better than 1.degree. C. The need to avoid such operating temperature limits, against a background of increasing accuracy requirements to match progress in data processing technology has given rise to the requirements for self-calibrating DACs to compensate reference resistor drift.
It is one objective of the present invention to provide a current source for a segment of a DAC in which the source current, made available by the segment in response to a digital code, is also continuously available for measurement. A further objective is to be able to alter the source current in the event of drift, so that the current in each segment can be maintained in a fixed or a known ratio relative to that in the other segments in response to measurements made on the current independently of the supply of current in the current source.
The present invention in one aspect comprises a current source for a digital-to-analogue converter (DAC) including an analogue current source, in which the DECS comprises a first source port which makes available a current to the current source and a second measurement port which makes available a current for measurement. Preferably the current available in the source port in the current source is equal to the current in the measurement port to within less than one least significant resolved bit of the DAC. In a further aspect of the invention the current source for a digital-to-analogue converter (DAC) comprises first and second current ports which allow delivery and measurement of current at the same time.
The present invention in a further aspect comprises a current source for a digital-to-analogue converter (DAC) as illustrated in FIG. 1 or described below. In one particular aspect the current source includes voltage controlled devices, such as an operational amplifier or a transconductance amplifier and a field effect transistor.
The present invention in a further aspect comprises a digital-to-analogue converter (DAC) having one or more switchable current sources having a predetermined current magnitude using a current source, in which the accuracy of the predetermined current in the source port is achieved by repeated correction in consequence of measurement of the current in the measurement port. In one configuration of the current source, correction is accomplished by repeated alteration of a reference voltage to compensate drift in the current source. In another configuration correction is accomplished by repeated alteration of a reference resistor to compensate drift in the current source.
In a further aspect of the invention, a digital-to-analogue converter (DAC) includes one or more switchable current sources having a predetermined current magnitude, in which accuracy of the predetermined current is achieved by measurement of the current in the measurement port of a current source and application of a correction digital code to a subsidiary digital-to-analogue converter which adds or subtracts a correction current to the current in the source port of the current source.
In a further aspect of the invention an analogue-to-digital converter (ADC) of the successive approximation type, incorporating single bit or multiple bit comparators or an ADC of the serial or serial/parallel type, includes a DAC using one or more switchable current sources having a predetermined current magnitude, comprising a current source in which current is available for measurement and for application in the DAC at the same time. Preferably the predetermined current is measured and corrected as indicated in the two paragraphs above.
In a further aspect of the invention there is provided a DAC including a current source having a current measurement port and a current source port, in which measurement of the current is made at the measurement port and information being a quantitative (digital) representation of the current at the source port is stored in a storage register and the information is used to correct or compensate for drift in the source current.
In a further aspect of the invention a non-binary DAC incorporates switchable current sources, including one or more current source in which the current magnitudes after consideration of the maximum expected drifts over the period of use of the DAC, are deliberately chosen so that the ratios of the magnitudes of adjacent currents are less than 2, and the most critical non-binary current magnitudes are measured and information being a quantitative (digital) representation of said currents are stored in a storage register. Further the invention includes an analogue-to-digital converter which comprises a non-binary DAC and a storage register which stores digital codes representative of the magnitudes of currents in the DAC.
The invention also concerns in another aspect, calibration circuits which may be used in a DAC. The precision of a self-calibrating DAC is specified by the precision of its calibrating circuit. When such a circuit is used to measure the relative magnitudes of the analogue quantities, for example, the currents, in each segment of the DAC the measured values can be used to restore the binary ratios periodically and compensate thermal drift or aging. Alternatively, in an analogue-to-digital converter (ADC) using a DAC, the multibit digital codes which are found by measurement to be the digital equivalents of the analogue quantities can be summed in the sequence designated by the comparator circuit to obtain the digital output code directly, without maintaining exact binary ratios between the segments in the event of drift.
The calibration circuits used normally comprise a capacitor and a stable current source which together generate a ramp voltage. The analogue outputs of the DAC are compared in sequence with the ramp voltage to measure their instantaneous values against a time base. It is recognised that serious accuracy problems are inherent in such circuits. Dielectric absorption in the capacitor, for example, has the effect that the instantaneous voltage across it is not truly proportional to the charge stored in it, the relationship in general being multi-modal. The delays, voltage offsets and common mode performance which are characteristic of amplifiers or comparators in the circuits also tend to vary owing to the fact that each reading is taken at a different voltage level of the ramp. Such component non-linearities or imperfections limit the measurement accuracy which may be ascribed to the calibration circuit. Drift and thermal noise in the components may also be the cause of measurement differences, particularly if the accuracy of a DAC exceeds 16 bits.
Another objective of the present invention is to provide a calibration circuit for a DAC, which is configured and operated so as to compensate or eliminate the significant measurement errors. These arise specifically from a multimodal ramp voltage characteristic from delays, voltage offsets or common mode performance which are characteristic of the circuit components, as well as from drift or noise which occurs between successive readings. A further objective is to provide a calibration circuit for a self-calibrating DAC, or for an ADC using a self-calibrating DAC, having a precision exceeding twenty significant bits.
According to a further aspect of the present invention, a calibration circuit for the set of current sources for a digital-to-analogue converter (DAC) comprises a resistor through which successively incremented current outputs of the DAC are during a period supplied to the output terminal of an integrator, a constant voltage source which applies a datum voltage to the non-inverting input terminal, and a constant current source which during the period supplies current to the inverting input terminal of the integrator. The integrator collects current at its output terminal to maintain its inverting input terminal to the datum voltage. The current increments correspond to an increase or decrease of the digital code applied to the DAC by one least significant bit.
According to a further aspect of the invention a calibration circuit for the set of current sources for a digital-to-analogue converter (DAC) comprises a comparator which compares the voltage at the resistor input terminal with the datum voltage during the application of successively incremented current outputs of the DAC applied to the circuit during the period, initiates the storage of a clock count record each time the comparator voltage difference reduces to a preselected or zero value, and initiates from the DAC the application of the incrementally next higher or lower source current. Preferably there are applied to the calibration circuit 2.sup.N successively incremented current outputs from a set of N current sources in the DAC and 2.sup.N clock count records are thereby obtained in the period.
In a further aspect of the invention there are obtained 2.sup.N clock count records from a set of N current sources in the calibration circuit during each period, and an estimate of the relative magnitude of the current in each source is obtained from the average of the 2.sup.N-1 count values derived in each period corresponding to that current increment.
In a further aspect of the invention the sign of the current applied to the integrator input terminal is alternately reversed in successive periods of use of the calibration circuit and the estimate of the relative magnitude of the current in each source is obtained from the average of 2.sup.N-1 count values derived in each of (two) such periods. Preferably the estimates of the relative magnitudes of the currents in the current sources, derived from the average of 2.sup.N-1 values of the clock count in each period, are scaled to normalise the estimate corresponding to the greatest current source.
In a further aspect of the invention the estimated currents derived in each period or each two successive periods are each further averaged recursively to present progressively latest best estimates of the relative magnitudes of the currents in the current sources.